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* Library of National Semiconductor Corp. JFET OP-AMP * Macromodels. Version 2.5 * * This library of macromodels is being supplied to users as * an aid to circuit designs. While it reflects reasonably * close similarity to the actual device in terms of * performance, it is not suggested as a replacement for * breadboarding. Simulation should be used as a supplement * to traditional lab testing. * * Users should very carefully note the following factors * regarding these models: * * -- Model performance in general will reflect typical * baseline specs for a given device, and certain aspects of * performance may not be modeled fully. * * -- While reasonable care has been taken in their * preparation, we cannot be responsible for correct * application on any and all computer systems. * * -- Model users are hereby notified that these models are * supplied "as is", with no direct or implied responsibility * on the part of National Semiconductor for their operation * within a customer circuit or system. Further, National * Semiconductor reserves the right to change these models * without prior notice. * * -- In all cases, the current data sheet information for a * given real device is your final design guideline, and is * the only actual performance guarantee. For further * technical information, refer to individual device data * sheets. * * Note: The current models presently do not simulate * temperature or noise effects. * * Your feedback and suggestions on these (and future) models * will be appreciated. * * Models developed by: * David Hindi * National Semiconductor For information on the models, contact: * 2900 Semiconductor Dr. Linear Applications * Santa Clara, CA 95052 (408) 721-3877 * M/S C2500 * FAX (408) 721-7321 For ordering information, contact: * Customer Response Center * (408) 721-4902 *--------------------------------------------------------- *////////////////////////////////////////////////////////// *LF155/A/B Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF155 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV *NOTE:Asymetrical slew rate not modeled. * ****************INPUT STAGE************** * IOS 2 1 3P *^Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=20 MHz C4 5 6 1.9894E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 1.65MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 3E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 9.6796E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=23.7 HZ C3 98 11 67.154P * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 9 1 VA8 26 27 0 R16 27 28 25 V5 28 25 -.1V D4 25 9 DX V4 24 28 -.1V D3 9 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12) * .ENDS *////////////////////////////////////////////////////////// *LF156/A/B Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF156 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV * ****************INPUT STAGE************** * IOS 2 1 3P *^Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=20 MHz C4 5 6 1.9894E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4.65MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 3E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 1.5944E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=31.96 HZ C3 98 11 49.9798P * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 9 1 VA8 26 27 0 R16 27 28 20 V5 28 25 -.25 D4 25 9 DX V4 24 28 -.25 D3 9 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12) * .ENDS *////////////////////////////////////////////////////////// *LF157/A/B Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF157 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV * ****************INPUT STAGE************** * IOS 2 1 3P *^Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=12 MHz C4 5 6 3.31573E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4.65MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 3E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 8.1291E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=224 HZ C3 98 11 7.10513P * ***************POLE STAGE*************** * *Fp3=42 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 8.3766E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 15 1 VA8 26 27 0 R16 27 28 25 V5 28 25 0.1V D4 25 15 DX V4 24 28 0.1V D3 15 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12) * .ENDS *////////////////////////////////////////////////////////// *LF255/A/B Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF255 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV *NOTE:Asymetrical slew rate not modeled. * ****************INPUT STAGE************** * IOS 2 1 3P *^Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=20 MHz C4 5 6 1.9894E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 1.65MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 3E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 9.6796E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=23.7 HZ C3 98 11 67.154P * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 9 1 VA8 26 27 0 R16 27 28 25 V5 28 25 -.1V D4 25 9 DX V4 24 28 -.1V D3 9 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12) * .ENDS *////////////////////////////////////////////////////////// *LF256/A/B Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF256 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV * ****************INPUT STAGE************** * IOS 2 1 3P *^Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=20 MHz C4 5 6 1.9894E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4.65MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 3E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 1.5944E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=31.96 HZ C3 98 11 49.9798P * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 9 1 VA8 26 27 0 R16 27 28 20 V5 28 25 -.25V D4 25 9 DX V4 24 28 -.25V D3 9 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12) * .ENDS *////////////////////////////////////////////////////////// *LF257/A/B Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF257 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV * ****************INPUT STAGE************** * IOS 2 1 3P *^Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=12 MHz C4 5 6 3.31573E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4.65MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 3E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 8.1291E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=224 HZ C3 98 11 7.10513P * ***************POLE STAGE*************** * *Fp3=42 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 8.3766E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 15 1 VA8 26 27 0 R16 27 28 25 V5 28 25 0.1V D4 25 15 DX V4 24 28 0.1V D3 15 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12) * .ENDS *////////////////////////////////////////////////////////// *LF351 Wide Bandwidth JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF351 1 2 99 50 28 * *Features: *Low supply current = 1.8mA *Wide bandwidth = 4MHz *High slew rate = 13V/uS *Low offset voltage = 10mV * ****************INPUT STAGE************** * IOS 2 1 25P *^Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=12 MHz C4 5 6 3.31573E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 1.7MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 5E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.13 D1 9 8 DX D2 10 9 DX V3 10 50 2.13 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 1.0985E7 G1 98 9 5 6 1E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=40.3 HZ C3 98 11 39.493P * ***************POLE STAGE*************** * *Fp3=42 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 3.7894E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 31.831M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 15 1 VA8 26 27 0 R16 27 28 35 V5 28 25 0.1V D4 25 15 DX V4 24 28 0.1V D3 15 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=50E-12) * .ENDS * *////////////////////////////////////////////////////////// *LF353 Wide Bandwidth Dual JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF353 1 2 99 50 28 * *Features: *Low supply current = 1.8mA *Wide bandwidth = 4MHz *High slew rate = 13V/uS *Low offset voltage = 10mV * *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * ****************INPUT STAGE************** * IOS 2 1 25P *^Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=12 MHz C4 5 6 3.31573E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 1.7MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 5E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.13 D1 9 8 DX D2 10 9 DX V3 10 50 2.13 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 1.0985E7 G1 98 9 5 6 1E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=40.3 HZ C3 98 11 39.493P * ***************POLE STAGE*************** * *Fp3=42 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 3.7894E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 31.831M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 15 1 VA8 26 27 0 R16 27 28 35 V5 28 25 0.1V D4 25 15 DX V4 24 28 0.1V D3 15 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=50E-12) * .ENDS * *////////////////////////////////////////////////////////// *LF355/A/B Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF355 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV *NOTE:Asymetrical slew rate not modeled. * ****************INPUT STAGE************** * IOS 2 1 3P *^Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=20 MHz C4 5 6 1.9894E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 1.65MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 3E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 9.6796E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=23.7 HZ C3 98 11 67.154P * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 9 1 VA8 26 27 0 R16 27 28 25 V5 28 25 -.1V D4 25 9 DX V4 24 28 -.1V D3 9 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12) * .ENDS *////////////////////////////////////////////////////////// *LF356/A/B Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF356 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV * ****************INPUT STAGE************** * IOS 2 1 3P *^Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=20 MHz C4 5 6 1.9894E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4.65MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 3E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 1.5944E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=31.96 HZ C3 98 11 49.9798P * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 9 1 VA8 26 27 0 R16 27 28 20 V5 28 25 -.25V D4 25 9 DX V4 24 28 -.25V D3 9 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12) * .ENDS *////////////////////////////////////////////////////////// *LF357/A/B Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF357 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV * ****************INPUT STAGE************** * IOS 2 1 3P *^Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=12 MHz C4 5 6 3.31573E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4.65MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 3E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 8.1291E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=224 HZ C3 98 11 7.10513P * ***************POLE STAGE*************** * *Fp3=42 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 8.3766E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 15 1 VA8 26 27 0 R16 27 28 25 V5 28 25 0.1V D4 25 15 DX V4 24 28 0.1V D3 15 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12) * .ENDS *////////////////////////////////////////////////////////// *LF400/A Fast-Settling JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF400 1 2 99 50 28 * *Features: *Fast settling time (.01%) = 400nS *High bandwidth = 16MHz *High slew rate = 60V/uS *Low offset voltage = .5mV *NOTE: High current output not modeled. * ****************INPUT STAGE************** * IOS 2 1 50P *^Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 1.0M J1 5 2 4 JX J2 6 7 4 JX R3 5 50 2K R4 6 50 2K *Fp2=100MHz C4 5 6 3.9789E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 10MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 .5E-3 1 *Input offset voltage.^ R8 99 49 40K R9 49 50 40K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 3.13 D1 9 8 DX D2 10 9 DX V3 10 50 3.13 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 6.887E6 G1 98 9 5 6 2.74E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=54.6 HZ C3 98 11 29.149P * ***************POLE STAGE*************** * *Fp3=100 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 1.5915E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1.0E-8 L2 98 17 144.7M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 15 1 VA8 26 27 0 R16 27 28 40 V5 28 25 .396V D4 25 15 DX V4 24 28 .396V D3 15 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-4 VTO=-2.00 IS=100E-12) * .ENDS * *////////////////////////////////////////////////////////// *LF411/A LOW OFFSET, LOW DRIFT JFET INPUT OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF411 1 2 99 50 28 * *Features: *Fast settling time (.01%) = 2uS *High bandwidth = 3MHz *High slew rate = 10V/uS *Low offset voltage = .5mV *Low supply current = 1.8mA * ****************INPUT STAGE************** * IOS 2 1 25.0P *^Input offset current CI1 1 0 3P CI2 2 0 3P R1 1 3 5E11 R2 3 2 5E11 I1 99 4 1.0M J1 5 2 4 JX J2 6 7 4 JX R3 5 50 650 R4 6 50 650 *Fp2=28 MHZ C4 5 6 4.372P * ***********COMMON MODE EFFECT*********** * I2 99 50 800UA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 .8E-3 1 *Input offset voltage.^ R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.13 D1 9 8 DX D2 10 9 DX V3 10 50 2.13 * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 9 5 6 20E-3 R5 98 9 10MEG VA3 9 11 0 *Fp1=18 HZ C3 98 11 857.516P * ***************POLE STAGE*************** * *Fp=30 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 5.305E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 144.7M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 15 1 VA8 26 27 0 R16 27 28 50 V5 28 25 0.646V D4 25 15 DX V4 24 28 0.646V D3 15 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.183E-3 VTO=-.65 IS=50E-12) * .ENDS *////////////////////////////////////////////////////////// *LF412/A LOW OFFSET, LOW DRIFT DUAL JFET INPUT OP-AMP MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF412 1 2 99 50 28 * *Features: *Fast settling time (.01%) = 2uS *High bandwidth = 3MHz *High slew rate = 10V/uS *Low offset voltage = 1mV *Low supply current = 1.8mA *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * ****************INPUT STAGE************** * IOS 2 1 25.0P *^Input offset current CI1 1 0 3P CI2 2 0 3P R1 1 3 5E11 R2 3 2 5E11 I1 99 4 1.0M J1 5 2 4 JX J2 6 7 4 JX R3 5 50 650 R4 6 50 650 *Fp2=28 MHZ C4 5 6 4.372P * ***********COMMON MODE EFFECT*********** * I2 99 50 800UA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 1E-3 1 *Input offset voltage.^ R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.13 D1 9 8 DX D2 10 9 DX V3 10 50 2.13 * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 9 5 6 20E-3 R5 98 9 10MEG VA3 9 11 0 *Fp1=18 HZ C3 98 11 857.516P * ***************POLE STAGE*************** * *Fp=30 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 5.305E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 144.7M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 15 1 VA8 26 27 0 R16 27 28 50 V5 28 25 0.646V D4 25 15 DX V4 24 28 0.646V D3 15 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.183E-3 VTO=-.65 IS=50E-12) * .ENDS *////////////////////////////////////////////////////////// *LF451 Wide-Bandwidth JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF451 1 2 99 50 28 * *Features: *Low supply current = 3.4mA(max) *Wide bandwidth = 4MHz *High slew rate = 13V/uS *Low offset voltage = 10mV * ****************INPUT STAGE************** * IOS 2 1 25P *^Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=12 MHz C4 5 6 3.31573E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 2.1MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 .3E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.13 D1 9 8 DX D2 10 9 DX V3 10 50 2.13 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 1.0985E7 G1 98 9 5 6 1E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=40.3 HZ C3 98 11 39.493P * ***************POLE STAGE*************** * *Fp3=42 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 3.7894E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 31.831M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 15 1 VA8 26 27 0 R16 27 28 35 V5 28 25 0.1V D4 25 15 DX V4 24 28 0.1V D3 15 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=50E-12) * .ENDS *////////////////////////////////////////////////////////// *LF453 Wide-Bandwidth Dual JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF453 1 2 99 50 28 * *Features: *Low supply current = 6.5mA(max) *Wide bandwidth = 4MHz *High slew rate = 13V/uS *Low offset voltage = 5mV(max) *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * ****************INPUT STAGE************** * IOS 2 1 25P *^Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=12 MHz C4 5 6 3.31573E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 2.1MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 .3E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.13 D1 9 8 DX D2 10 9 DX V3 10 50 2.13 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 1.0985E7 G1 98 9 5 6 1E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=40.3 HZ C3 98 11 39.493P * ***************POLE STAGE*************** * *Fp3=42 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 3.7894E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 31.831M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 15 1 VA8 26 27 0 R16 27 28 35 V5 28 25 0.1V D4 25 15 DX V4 24 28 0.1V D3 15 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=50E-12) * .ENDS